
2011-2012 Microchip Technology Inc.
Preliminary
DS61168D-page 101
PIC32MX1XX/2XX
REGISTER 8-3:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
R/W-0
—
RODIV<14:8>(3)
23:16
R/W-0
RODIV<7:0>(3)
15:8
R/W-0
U-0
R/W-0
U-0
R/W-0, HC
R-0, HS, HC
ON
—SIDL
OE
RSLP(2)
—
DIVSWEN
ACTIVE
7:0
U-0
R/W-0
—
ROSEL<3:0>(1)
Legend:
HC = Hardware Clearable HS = Hardware Settable
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Unimplemented: Read as ‘0’
bit 30-16 RODIV<14:0> Reference Clock Divider bits(1)
111111111111111 = Output clock is source clock frequency divided by 65,534
111111111111110 = Output clock is source clock frequency divided by 65,532
000000000000010 = Output clock is source clock frequency divided by 4
000000000000001 = Output clock is source clock frequency divided by 2
000000000000000 = Output clock is same frequency as source clock (no divider)
bit 15
ON: Output Enable bit
1 = Reference Oscillator Module enabled
0 = Reference Oscillator Module disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
SIDL: Peripheral Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12
OE: Reference Clock Output Enable bit
1 = Reference clock is driven out on REFCLKO pin
0 = Reference clock is not driven out on REFCLKO pin
bit 11
RSLP: Reference Oscillator Module Run in Sleep bit(2)
1 = Reference Oscillator Module output continues to run in Sleep
0 = Reference Oscillator Module output is disabled in Sleep
bit 10
Unimplemented: Read as ‘0’
bit 9
DIVSWEN: Divider Switch Enable bit
1 = Divider switch is in progress
0 = Divider switch is complete
bit 8
ACTIVE: Reference Clock Request Status bit
1 = Reference clock request is active
0 = Reference clock request is not active
Note 1: The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may
result.
2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.
3: While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to’1’.